Precise clocks are necessary for demanding telecom applications. Digital-Subscriber Lines (DSLs) in particular operate at high data rates and clocks must be precisely extracted from the line signal. The extracted clock is used to time the analog-to-digital converter in the receiver, or the digital-to-analog converter (DAC) in the transmitter. Of course, many other applications also require precise clocks.
The clock may need to be adjusted to stay in sync with the incoming line signal. A Phase-locked loop (PLL) could be used, but precise adjustments may be more conveniently produced without noise accumulation with a delay-locked loop (DLL). While a PLL changes the generated clock by adjusting a voltage input to a voltage-controlled oscillator (VCO), the DLL adjusts the generated clock by adjusting a bias voltage to a series of buffers.
Adjusting the bias voltage changes the delay through each of the buffers in the DLL. When the buffers are all identical, the period of the generated clock is divided into N equal phases, where N is the number of buffers in the series. A multiplexer can be used to select one of the N phases as the generated clock. Changing which buffer's output is selected by the multiplexer changes the phase of the generated clock. Stepping through a series of phases gradually reduces or increases the clock period, thus changing the frequency of the generated clock.
FIG. 1 is a diagram of a prior-art delay-locked loop (DLL). An input clock ICLK is generated from a constant-frequency source such as from a crystal oscillator. A series of buffers 12 receive ICLK, and each successive buffer 12 delays ICLK by an additional buffer delay. The buffer delay is the same for all buffers 12, but the buffer delay may be adjusted by changing a bias voltage produces by bias generator 18. The bias voltage may be applied to a gate of a complementary metal-oxide-semiconductor (CMOS) transistor that acts as a current source or sink to alter the current through each buffer 12, and thus alter the delay to charge or discharge each buffer's output.
The output of the final buffer 12 in the series is the final delayed clock DCLK. DCLK is input to phase comparator 14 and compared to ICLK, the other input to phase comparator 14. Phase comparator 14 generates an output when the edge of ICLK does not occur simultaneously with the edge of DCLK. A positive or a negative output can be generated. Charge pump 16 responds to the output of phase comparator 14 by charging or discharging a filter capacitor (not shown). The voltage across the filter capacitor from charge pump 16 is input to bias generator 18. Bias generator 18 responds by generating the bias voltage from the input voltage and buffering its bias-voltage output to buffers 12.
When the phase of DCLK varies from that of ICLK, phase comparator 14 commands charge pump 16 to adjust the bias voltage to buffers 12. The delay through buffers 12 changes until the delay through the series of buffers 12 is exactly one period of ICLK.
When the phase of DCLK matches ICLK, the DLL becomes stable and the average bias voltage is no longer adjusted. Any variations in ICLK or DCLK are compensated for by altering the bias voltage until DCLK matches ICLK.
When all buffers 12 are identical, the ICLK period is exactly divided into N phases. Each buffer 12 outputs a clock that is delayed from ICLK. Mux 20 can be used to select one of these outputs as the generated clock. The phase of the generated clock can be any phase with the ICLK period divided by N. Selecting an output from one of the later buffers in the series increase the phase delay of the generated clock, while selecting an output from an earlier buffer in the series reduces the phase delay.
Sometimes a very precise clock is to be generated, requiring fine phase adjustments. For example, adjustments of only 1/128t.sup.h of the clock period are desired. The DLL requires 128 buffers (N=128) to divide the input clock ICLK into 128 phases. Mux 20 has 128 inputs so that any of the 128 phases can be selected as the generated clock.
Such precision requires a large number of buffers and a large mux. To prevent glitches, each of the buffer outputs may need to be latched. Thus 128 latches, buffers, and mux-inputs are required in this example. Such large numbers of components increases the area, cost, and power consumption of an integrated circuit (IC) containing such a precise DLL.
Array of DLLs--FIG. 2
An alternative for a high-precision DLL is presented by Christiansen in "An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops", IEEE JSSCC, vol. 31, No. 7, July 1996. FIG. 2 shows a prior-art array of DLL's for generating precise clocks. A coarse DLL 24 receives the input clock ICLK and divides it into several sub-clocks. The phase detector (PD) includes not only phase comparator 14 of FIG. 1, but also charge pump 16 and bias generator 18. A single PD component is shown for simplicity.
Each of the sub-clocks from coarse DLL 24 is input to a fine DLL 22. Each of the fine DLLs 22 is a standard DLL with a series of buffers that generate a delayed clock that is compared to the input sub-clock by a phase detector PD. Thus each of the fine DLLs 22 divides the coarse-delayed sub-clock into multiple phases. In practice, fine DLLs 22 have many more buffer stages than coarse DLL 24. Coarse DLL 24 provides a relatively large initial phase shift, then fine DLLs 22 divide the sub-clocks into many smaller phases.
Note that all of the DLLs 22, 24 operate at the same frequency of the input clock ICLK. The fine DLLs 22 merely are phase-shifted relative to ICLK by coarse DLL 24. A large number of components is still required, since many fine DLLs 22 are required. For example, when coarse DLL 24 has four buffers, four fine DLLs 22 are required. Large multiplexers and latches are likely to be needed as well.
What is desired is a DLL for generating a high-precision clock. It is desired to adjust the phase of the generated clock in many increments of the input-clock period. Although many phases may be selected, it is desired to use fewer latches and components. It is desired to reduce the size of a DLL while still generating fine phase adjustments. Muxes with fewer inputs are desired for generating a precisely-adjusted clock. It is desired to eliminate the array of DLLs and instead use just two DLLs.